Integrated circuits are an integral part of virtually any electronic device. A variety of integrated circuits are often used together to enable the operation of the electronic device. While integrated circuits are typically designed for a particular application, one type of integrated circuit that enables flexibility is a programmable logic device. A programmable logic device (PLD) is designed to be user-programmable so that users may implement logic designs of their choices. One type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” having a two-level AND/OR structure connected together and to input/output (I/O) resources by an interconnect switch matrix. Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
A programmable logic device may be used in a wide variety of applications that are implemented with a variety of operating systems. Accordingly, the operation of the programmable logic device may vary depending upon the operating system. One common use for programmable logic devices is in the transmission of data. For most data transfers in a system employing a microprocessor, bursting of data in the native bus data width of the microprocessor is the most efficient mechanism for transmitting data. Data that is part of a burst transfer, such as data transferred by direct memory access (DMA) devices, is generally transferred in ascending address order. Valid data bytes are adjacent to each other during any transfer cycle such that no invalid data bytes are included between valid data bytes. A transfer cycle is either a single data beat transaction or a single burst transaction comprised of multiple data beats.
DMA transfers performed in hardware as part of a microprocessor system are often inefficient when the source and destination data buffers are not address aligned to the native data width of the microprocessor data bus. The problem of mis-aligned data buffers is often encountered when off-the-shelf operating systems, such as MontaVista Linux by Montavista Software or VxWorks 5.x by Wind River, are used. These operating systems, while popular with microprocessor system implementers, generally do not allow the end user to specify data buffer alignment within a system implementation. Accordingly, the data must be realigned by the user. This data realignment may be performed in a number of ways. For example, the realignment may require the user to include additional programming to detect when a data buffer is not aligned, and then employ the microprocessor to copy the unaligned buffer to an aligned buffer prior to initiating a DMA transfer of that buffer. Alternatively, a DMA device may transfer data in bit widths that are less than the microprocessor data bus width but are guaranteed to meet all possible buffer alignments.
However, many applications for receiving data require that data that is transmitted as aligned data be realigned by the receiver to correspond to the original unaligned data. In order to realign the data, conventional devices require buffer copies maintained by the processor, and therefore reduce system performance. That is, the DMA device would have to transfer data into a word aligned memory, and then signal the processor to copy that aligned data to an unaligned final destination. Such a requirement to transfer data into a word aligned memory significantly minimizes overall system performance by occupying the processor with a low-level task.
Accordingly, there is a need for an improved circuit for and method of realigning data by a receiver in a data communication system.